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D a t a S h e e t , V 1. 0 , N o v . 20 0 3
C161S
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er
M i c r o c o n t r o l l er s
Never
stop
thinking.
Edition 2003-11 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany
(c) Infineon Technologies AG 2004.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , V 1. 0 , N o v . 20 0 3
C161S
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er
M i c r o c o n t r o l l er s
Never
stop
thinking.
C161S Revision History: Previous Version: Page 2003-11 none V1.0
Subjects (major changes since last revision)
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Template: mc_tmplt_a5.fm / 3 / 2003-09-01
16-Bit Single-Chip Microcontroller C166 Family C161S
C161S
1
*
Summary of Features
High Performance 16-bit CPU with 4-Stage Pipeline - 80 ns Instruction Cycle Time at 25 MHz CPU Clock - 400 ns Multiplication (16 x 16 bit), 800 ns Division (32 / 16 bit) - Enhanced Boolean Bit Manipulation Facilities - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Single-Cycle Context Switching Support - 16 Mbytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area 16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down to 40 ns 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input On-Chip Memory Modules: 2 Kbytes On-Chip Internal RAM (IRAM) On-Chip Peripheral Modules - Two Multi-Functional General Purpose Timer Units with 5 Timers - Two Serial Channels (Sync./Asynchronous and High-Speed-Synchronous) - On-Chip Real Time Clock External Address Space for Code and Data - Programmable External Bus Characteristics for Different Address Ranges - Multiplexed or Demultiplexed External Address/Data Buses with 8-bit or 16-bit Data Bus Width - Four Programmable Chip-Select Signals - 4 Mbytes maximum address window size, results in a total external address space of 16 Mbytes, when all chip-select signal (address windows) are active Idle and Power Down Modes with Flexible Power Management Programmable Watchdog Timer and Oscillator Watchdog Up to 63 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis Power Supply: the C161S can operate from a 5 V or a 3 V power supply (see Table 1) Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 80-Pin MQFP Package
1 V1.0, 2003-11
* * * * *
*
* * * * *
* *
Data Sheet
C161S
Summary of Features This document describes several derivatives of the C161 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 Derivative SAB-C161S-L25M SAF-C161S-L25M SAB-C161S-LM3V SAF-C161S-LM3V C161S Derivative Synopsis Max. Operating Frequency 25 MHz 25 MHz 20 MHz 20 MHz Operating Voltage 4.5 to 5.5 V (Standard) 4.5 to 5.5 V (Standard) 3.0 to 3.6 V (Reduced) 3.0 to 3.6 V (Reduced) Ambient Temperature 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C
For simplicity all versions are referred to by the term C161S throughout this document. Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery.
For the available ordering codes for the C161S please refer to the "Product Catalog Microcontrollers", which summarizes all available microcontroller variants. Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code.
Data Sheet
2
V1.0, 2003-11
C161S
General Device Information
2
2.1
General Device Information
Introduction
The C161S is a derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides clock generation via PLL and power management features. The C161S is especially suited for cost sensitive applications.
VDD
VSS
XTAL1 XTAL2 RSTIN RSTOUT NMI EA ALE RD WR/WRL Port 5 2 bit
MCA05504
PORT0 16 bit PORT1 16 bit Port 2 7 bit C161S Port 3 12 bit Port 4 6 bit Port 6 4 bit
Figure 1
Logic Symbol
Data Sheet
3
V1.0, 2003-11
C161S
General Device Information
2.2
Pin Configuration and Definition
P5.15/T2EUD P5.14/T4EUD P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN
VSS
XTAL1 XTAL2
VDD
P4.4/A20 P4.5/A21 RD WR/WRL ALE EA P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7
P0H.0/AD8 P0H.1/AD9
VSS VDD
VDD VSS
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P1H.7/A15 P1H.6/A14 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VDD VSS
C161S
P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10
MCP05505
Figure 2
Pin Configuration (top view)
Data Sheet
4
V1.0, 2003-11
C161S
General Device Information Table 2 Symbol Pin No. XTAL1 XTAL2 2 3 Pin Definitions and Functions Input Function Outp. I O XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics (see Chapter 5.4) must be observed. Port 3 is a 12-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The following Port 3 pins also serve for alternate functions: CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Control Input T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp. T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp. MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) BHE External Memory High Byte Enable Signal, External Memory High Byte Write Strobe WRH SCLK SSC Master Clock Output / Slave Clock Input. Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 4 can be used to output the segment address lines: A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line A21 Segment Address Line
P3
IO
P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P4
5 6 7 8 9 10 11 12 13 14 15 16
I O I I I I I/O I/O O I/O O O I/O IO
P4.0 P4.1 P4.2 P4.3 P4.4 P4.5
17 18 19 20 23 24
O O O O O O
Data Sheet
5
V1.0, 2003-11
C161S
General Device Information Table 2 Symbol Pin No. RD WR/ WRL 25 26 Pin Definitions and Functions (cont'd) Input Function Outp. O O External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the C161S to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. "ROMless" versions must have this pin tied to `0'. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15
ALE
27
O
EA
28
I
PORT0 P0L.0-7
IO 29-36
P0H.0-7 39-46
Data Sheet
6
V1.0, 2003-11
C161S
General Device Information Table 2 Symbol Pin No. PORT1 P1L.0-7 47-54 Pin Definitions and Functions (cont'd) Input Function Outp. IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C161S. An internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table. Note: To let the reset configuration of PORT0 settle and to let the PLL lock a reset duration of approx. 1 ms is recommended. RST OUT 66 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161S to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally.
P1H.0-7 55-62
RSTIN
65
I/O
NMI
67
I
Data Sheet
7
V1.0, 2003-11
C161S
General Device Information Table 2 Symbol Pin No. P6 Pin Definitions and Functions (cont'd) Input Function Outp. IO Port 6 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The Port 6 pins also serve for alternate functions: CS0 Chip Select 0 Output Chip Select 1 Output CS1 Chip Select 2 Output CS2 CS3 Chip Select 3 Output Port 2 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The following Port 2 pins also serve for alternate functions: EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input Port 5 is a 2-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as timer inputs: T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Input T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Input Digital Supply Voltage: + 5 V during normal operation and idle mode. + 3.3 V during reduced supply operation and idle mode. 2.5 V during power down mode. Note: Please refer to the Operating Conditions Parameters. Digital Ground.
P6.0 P6.1 P6.2 P6.3 P2
68 69 70 71
O O O O IO
P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 P5 P5.14 P5.15
72 73 74 75 76 77 78
I I I I I I I I
79 80 4, 22, 37, 64
I I -
VDD
VSS
1, 21, 38, 63
-
Data Sheet
8
V1.0, 2003-11
C161S
General Device Information Note: The following behavioural differences must be observed when the bidirectional reset is active: * * * * * Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. The reset indication flags always indicate a long hardware reset. The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. Pin RSTIN may only be connected to external reset devices with an open drain output driver. A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
9
V1.0, 2003-11
C161S
Functional Description
3
Functional Description
The architecture of the C161S combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the onchip memory blocks allow the design of compact systems with maximum performance. Figure 3 gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161S. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section).
Data
Dual Port
ProgMem
Internal ROM Area
32
Instr. / Data
C166-Core
16 16
IRAM
Internal RAM 2 Kbytes
CPU
Data
16
External Instr. / Data
PEC
Osc / PLL RTC
16
XTAL
Interrupt Controller 16-Level Priority
WDT
On-Chip XBUS (16-Bit Demux)
Interrupt Bus
16
Peripheral Data Bus
ASC0
(USART)
SSC
(SPI)
GPT
T2 T3 T4 T5
Port 4
6
EBC
XBUS Control External Bus Control
Port 0 16 Port 1 16
Port 6
4
BRGen
BRGen Port 3 12
T6 Port 5 2
MCB04323_1S.vsd
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).
Data Sheet
10
V1.0, 2003-11
Port 2
7
C161S
Functional Description
3.1
Memory Organization
The memory space of the C161S is configured in a von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 Mbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C161S is prepared to incorporate on-chip program memory (not in the ROM-less derivatives, of course) for code or constant data. The internal ROM area can be mapped either to segment 0 or segment 1. 2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 x 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external RAM and/or ROM can be connected to the microcontroller. The maximum contiguous external address space is 4 Mbytes, i.e. this is the maximum address window size. Using the chip-select lines (multiple windows) this results in a maximum usable external address space of 16 Mbytes.
Data Sheet
11
V1.0, 2003-11
C161S
Functional Description
3.2
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: * * * * 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 4 external CS signals (3 windows plus default) can be generated in order to save external glue logic. The C161S offers the possibility to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is switched off and the CS signals are directly generated from the address. The unlatched CS mode is enabled by setting CSCFG (SYSCON.6). For applications which require less than 4 Mbytes of external memory space, this address space can be restricted to 1 Mbyte, 256 Kbytes, or to 64 Kbytes. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if the full address width is used.
Data Sheet
12
V1.0, 2003-11
C161S
Functional Description
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161S's instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU SP STKOV STKUN Exec. Unit Instr. Ptr. Instr. Reg. 32 ROM 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr. MDH MDL Mul/Div-HW Bit-Mask Gen ALU (16-bit) Barrel - Shifter Context Ptr. ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 Registers
16 Internal RAM R15
General Purpose
R15
R0
16
MCB02147
Figure 4
CPU Block Diagram
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.
Data Sheet
13
V1.0, 2003-11
C161S
Functional Description A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161S instruction set which includes the following instruction classes: * * * * * * * * * * * * Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Data Sheet
14
V1.0, 2003-11
C161S
Functional Description
3.3.1
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161S is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C161S supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161S has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 3 shows all of the possible C161S interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Note: Interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).
Data Sheet
15
V1.0, 2003-11
C161S
Functional Description Table 3 C161S Interrupt Nodes Enable Flag CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE XP0IE XP1IE XP2IE XP3IE CC29IE CC30IE CC31IE
16
Source of Interrupt or Request PEC Service Request Flag Unassigned node External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Reg. Unassigned node Unassigned node ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error Unassigned node Unassigned node Unassigned node PLL/OWD and RTC Unassigned node Unassigned node Unassigned node
Data Sheet
Interrupt Vector CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT XP0INT XP1INT XP2INT XP3INT CC29INT CC30INT CC31INT
Vector Location 00'0060H 00'0064H 00'0068H 00'006CH 00'0070H 00'0074H 00'0078H 00'007CH 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A0H 00'00A4H 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'0100H 00'0104H 00'0108H 00'010CH 00'0110H 00'0114H 00'0118H
Trap Number 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 22H 23H 24H 25H 26H 27H 28H 29H 2AH 47H 2BH 2CH 2DH 2EH 2FH 40H 41H 42H 43H 44H 45H 46H
V1.0, 2003-11
CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR XP0IR XP1IR XP2IR XP3IR CC29IR CC30IR CC31IR
C161S
Functional Description The C161S also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 4 shows all of the possible exceptions or error conditions that can arise during runtime: Table 4 Hardware Trap Summary Trap Flag Trap Vector RESET RESET RESET NMITRAP STOTRAP STUTRAP Vector Location 00'0000H 00'0000H 00'0000H 00'0008H 00'0010H 00'0018H Trap Number 00H 00H 00H 02H 04H 06H Trap Priority III III III II II II
Exception Condition
Reset Functions: - * Hardware Reset * Software Reset * W-dog Timer Overflow Class A Hardware Traps: * Non-Maskable Interrupt * Stack Overflow * Stack Underflow Class B Hardware Traps: * Undefined Opcode * Protected Instruction Fault * Illegal Word Operand Access * Illegal Instruction Access * Illegal External Bus Access Reserved Software Traps * TRAP Instruction NMI STKOF STKUF
UNDOPC PRTFLT ILLOPA ILLINA ILLBUS - -
BTRAP BTRAP BTRAP BTRAP BTRAP - -
00'0028H 00'0028H 00'0028H 00'0028H 00'0028H [2CH - 3CH]
0AH 0AH 0AH 0AH 0AH [0BH - 0FH]
I I I I I - Current CPU Priority
Any Any [00'0000H - [00H - 00'01FCH] 7FH] in steps of 4H
17
Data Sheet
V1.0, 2003-11
C161S
Functional Description
3.4
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.
Data Sheet
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V1.0, 2003-11
C161S
Functional Description
T2EUD fCPU T2IN 2n : 1 T2 Mode Control
U/D GPT1 Timer T2 Interrupt Request
Reload Capture Interrupt Request T3 Mode Control Toggle FF GPT1 Timer T3 U/D Other Timers Capture Reload T3OTL T3OUT
fCPU
2 :1
n
T3IN
T3EUD
T4IN fCPU T4EUD 2n : 1
T4 Mode Control
GPT1 Timer T4 U/D
Interrupt Request
MCT02141
n = 3 ... 10 Figure 5 Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows the C161S to measure absolute time differences or to perform pulse multiplication without software overhead.
Data Sheet
19
V1.0, 2003-11
C161S
Functional Description The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.
Interrupt Request (T5IR)
fSYS
2n : 1 T5 Mode Control
GPT2 Timer T5 U/D Clear Capture
T3IN/ MUX CAPIN
GPT2 CAPREL
Interrupt Request (CRIR) Interrupt Request (T6IR)
CT3 Clear fSYS 2n : 1 T6 Mode Control GPT2 Timer T6 U/D
Toggle FF
T6OTL
Mcb03999_x1s.vsd
n=2...9 Figure 6 Block Diagram of GPT2
Data Sheet
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V1.0, 2003-11
C161S
Functional Description
3.5
Real Time Clock
The Real Time Clock (RTC) module of the C161S consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32) and is therefore independent from the selected clock generation mode of the C161S. All timers count up. The RTC module can be used for different purposes: * * * System clock to determine the current time and date Cyclic time based interrupt 48-bit timer for long term measurements
T14REL Reload T14 8:1 f RTC Interrupt Request RTCH RTCL
MCD04432
Figure 7
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to maintain the correct system time even when intermediate resets are executed.
Data Sheet
21
V1.0, 2003-11
C161S
Functional Description
3.6
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 625 kbit/s and half-duplex synchronous communication at up to 2.5 Mbit/s (@ 20 MHz CPU clock). A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake-up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 5 Mbit/s (@ 20 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception, and error handling three separate interrupt vectors are provided. The SSC transmits or receives characters of 2 ... 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
22
V1.0, 2003-11
C161S
Functional Description
3.7
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 s and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz).
3.8
Parallel Ports
The C161S provides up to 63 I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17 ... A16 in systems where segmentation is enabled to access more than 64 Kbytes of memory. Port 6 provides optional chip select signals. Port 3 includes alternate functions of timers, serial interfaces, and the optional bus control signal BHE. Port 5 is used for timer control signals.
Data Sheet
23
V1.0, 2003-11
C161S
Functional Description
3.9
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency. In direct drive mode the PLL base frequency is used directly (fCPU = 2 ... 5 MHz). In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 ... 2.5 MHz). Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON. In this case (OWDDIS = `1') the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also no interrupt request will be generated in case of a missing oscillator clock. Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time. Thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the RD line low upon a reset, similar to the standard reset configuration via PORT0.
Data Sheet
24
V1.0, 2003-11
C161S
Functional Description
3.10
Power Management
The C161S provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): * Power Saving Modes switch the C161S into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Power Down Mode stops all clock signals and all operation (RTC may optionally continue running). Clock Generation Management controls the distribution and the frequency of internal and external clock signals (control via register SYSCON2). Slow Down Mode lets the C161S run at a CPU clock frequency of fOSC / 1 ... 32 (half for prescaler operation) which drastically reduces the consumed power. The PLL can be optionally disabled while operating in Slow Down Mode. Peripheral Management permits temporary disabling of peripheral modules (control via register SYSCON3). Each peripheral can separately be disabled/enabled. A group control option disables a major part of the peripheral set by setting one single bit.
*
*
The on-chip RTC supports intermittent operation of the C161S by generating cyclic wake-up signals. This offers full performance to quickly react on action requests while the intermittent sleep phases greatly reduce the average power consumption of the system.
Data Sheet
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V1.0, 2003-11
C161S
Functional Description
3.11
Instruction Set Summary
Table 5 lists the instructions of the C161S in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C166 Family Instruction Set Manual". This document also provides a detailed description of each instruction. Table 5 Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR
Data Sheet
Instruction Set Summary Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16- x 16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR
26
Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2
V1.0, 2003-11
C161S
Functional Description Table 5 Instruction Set Summary (cont'd) Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP
Data Sheet
27
V1.0, 2003-11
C161S
Functional Description
3.12
Special Function Registers Overview
Table 6 lists all SFRs which are implemented in the C161S in alphabetical order. The following markings assist in classifying the listed registers: "b" in the "Name" column marks Bit-addressable SFRs. "E" in the "Physical Address" column marks (E)SFRs in the Extended SFR-Space. "X" in the "Physical Address" column marks registers within on-chip X-peripherals. Table 6 Name ADCIC ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC BUSCON0 BUSCON1 BUSCON2 BUSCON3 BUSCON4 CAPREL CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC CC29IC CC30IC CC31IC CC8IC CC9IC C161S Registers, Ordered by Name Physical Address b FF98H FE18H FE1AH FE1CH FE1EH b FF9AH b FF0CH b FF14H b FF16H b FF18H b FF1AH FE4AH b FF8CH b FF8EH b FF90H b FF92H b FF94H b FF96H b F184H b F194H b FF88H b FF8AH 8-Bit Description Addr. CCH 0CH 0DH 0EH 0FH CDH 86H 8AH 8BH 8CH 8DH 25H C6H C7H C8H C9H CAH CBH E C2H E CAH C4H C5H Software Interrupt Control Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 Software Interrupt Control Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register EX2IN Interrupt Control Register EX3IN Interrupt Control Register EX4IN Interrupt Control Register EX5IN Interrupt Control Register EX6IN Interrupt Control Register EX7IN Interrupt Control Register Software Interrupt Control Register Software Interrupt Control Register Software Interrupt Control Register Software Interrupt Control Register EX1IN Interrupt Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0XX0H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
b F18CH E C6H
Data Sheet
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C161S
Functional Description Table 6 Name CP CRIC CSP DP0H DP0L DP1H DP1L DP2 DP3 DP4 DP6 DPP0 DPP1 DPP2 DPP3 EXICON IDCHIP IDMANUF IDMEM IDMEM2 IDPROG ISNC MDC MDH MDL ODP2 ODP3 ODP6 ONES P0H
Data Sheet
C161S Registers, Ordered by Name (cont'd) Physical Address FE10H b FF6AH FE08H b F102H b F100H b F106H b F104H b FFC2H b FFC6H b FFCAH b FFCEH FE00H FE02H FE04H FE06H 8-Bit Description Addr. 08H B5H 04H E 81H E 80H E 83H E 82H E1H E3H E5H E7H 00H 01H 02H 03H CPU Context Pointer Register GPT2 CAPREL Interrupt Ctrl. Reg. CPU Code Seg. Pointer Reg. (read only) P0H Direction Control Register P0L Direction Control Register P1H Direction Control Register P1L Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register CPU Data Page Pointer 0 Reg. (10 bits) CPU Data Page Pointer 1 Reg. (10 bits) CPU Data Page Pointer 2 Reg. (10 bits) CPU Data Page Pointer 3 Reg. (10 bits) External Interrupt Control Register Identifier Identifier Identifier Identifier Identifier Interrupt Subnode Control Register CPU Multiply Divide Control Register CPU Multiply Divide Reg. - High Word CPU Multiply Divide Reg. - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Constant Value 1's Register (read only) Port 0 High Reg. (Upper half of PORT0)
29
Reset Value FC00H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 00H 00H 0000H 0001H 0002H 0003H 0000H 05XXH 1820H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00H FFFFH 00H
b F1C0H E E0H F07CH E 3EH F07EH F07AH F076H F078H b FF0EH FE0CH FE0EH E 3FH E 3DH E 3BH E 3CH 87H 06H 07H
b F1DEH E EFH
b F1C2H E E1H b F1C6H E E3H b F1CEH E E7H b FF1EH b FF02H 8FH 81H
V1.0, 2003-11
C161S
Functional Description Table 6 Name P0L P1H P1L P2 P3 P4 P5 P6 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW RP0H RTCH RTCL S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC C161S Registers, Ordered by Name (cont'd) Physical Address b FF00H b FF06H b FF04H b FFC0H b FFC4H b FFC8H b FFA2H b FFCCH FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF10H b F108H 8-Bit Description Addr. 80H 83H 82H E0H E2H E4H D1H E6H 60H 61H 62H 63H 64H 65H 66H 67H 88H E 84H Port 0 Low Reg. (Lower half of PORT0) Port 1 High Reg. (Upper half of PORT1) Port 1 Low Reg.(Lower half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 6 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register CPU Program Status Word System Startup Config. Reg. (Rd. only) RTC High Register RTC Low Register Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Ctrl. Reg Serial Channel 0 Receive Buffer Reg. (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Reset Value 00H 00H 00H 0000H 0000H 00H XXXXH 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXH XXXXH XXXXH 0000H 0000H 0000H XXH 0000H 0000H
F0D6H E 6BH F0D4H E 6AH FEB4H b FFB0H b FF70H FEB2H b FF6EH 5AH D8H B8H 59H B7H
b F19CH E CEH
Data Sheet
30
V1.0, 2003-11
C161S
Functional Description Table 6 Name S0TBUF S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON SYSCON2 SYSCON3 T14 T14REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON C161S Registers, Ordered by Name (cont'd) Physical Address FEB0H b FF6CH FE12H F0B4H b FFB2H b FF76H F0B2H b FF74H F0B0H b FF72H FE14H FE16H b FF12H 8-Bit Description Addr. 58H B6H 09H E 5AH D9H BBH E 59H BAH E 58H B9H 0AH 0BH 89H Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer SSC Receive Interrupt Control Register SSC Transmit Buffer SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CPU System Configuration Register 2 CPU System Configuration Register 3 RTC Timer 14 Register RTC Timer 14 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register
1)
Reset Value 00H 0000H FC00H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H FA00H FC00H 0XX0H 0000H 0000H XXXXH XXXXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
V1.0, 2003-11
b F1D0H E E8H b F1D4H E EAH F0D2H E 69H F0D0H E 68H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H FE46H b FF46H 20H A0H B0H 21H A1H B1H 22H A2H B2H 23H A3H
Data Sheet
31
C161S
Functional Description Table 6 Name T5IC T6 T6CON T6IC TFR WDT WDTCON XP0IC XP1IC XP2IC XP3IC ZEROS C161S Registers, Ordered by Name (cont'd) Physical Address b FF66H FE48H b FF48H b FF68H b FFACH FEAEH b FFAEH b F186H b F18EH b F196H b F19EH b FF1CH 8-Bit Description Addr. B3H 24H A4H B4H D6H 57H D7H E C3H E C7H E CBH E CFH 8EH GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register Software Interrupt Control Register Software Interrupt Control Register Software Interrupt Control Register RTC/PLL Interrupt Control Register Constant Value 0's Register (read only)
2)
Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 00XXH 0000H 0000H 0000H 0000H 0000H
1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source.
Data Sheet
32
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C161S
Electrical Parameters
4
4.1
Table 7 Parameter
Electrical Parameters
Absolute Maximum Ratings
Absolute Maximum Rating Parameters Symbol Limit Values Min. Max. 150 150 6.5 -65 -40 -0.5 -0.5 -10 - Unit Notes
Storage temperature Junction temperature Voltage on VDD pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation
TST TJ VDD VIN IOV
|IOV|
C C
V
- under bias - - - -
VDD + 0.5 V
10 100 mA mA
PDISS
-
1.5
W
-
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
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C161S
Electrical Parameters
4.2
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation of the C161S. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 8 Parameter Standard digital supply voltage Reduced digital supply voltage Digital ground voltage Overload current Operating Condition Parameters Symbol Limit Values Min. Max. 5.5 5.5 3.6 3.6 V V V V V mA mA pF Active mode, fCPUmax = 25 MHz Power down mode Active mode, fCPUmax = 20 MHz Power down mode Reference voltage Per pin2)3)
3)
Unit
Notes
VDD
4.5 2.51)
VDD
3.0 2.51)
VSS IOV
0 - - - 0 -40 -40
5
50 100 70 85 125
Absolute sum of overload |IOV| currents External Load Capacitance Ambient temperature
CL TA
- SAB-C161S ... SAF-C161S ... SAK-C161S ...
C C C
1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode. 2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR, etc. 3) Not subject to production test, verified by design/characterization.
Data Sheet
34
V1.0, 2003-11
C161S
Electrical Parameters
4.3
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C161S and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C161S will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C161S.
Data Sheet
35
V1.0, 2003-11
C161S
Electrical Parameters
4.4
Table 9 Parameter
DC Parameters
DC Characteristics (Standard Supply Voltage Range) (Operating Conditions apply)1) Symbol Limit Values Min. Max. 0.2 VDD V - 0.1 - - - - - Unit Test Condition
Input low voltage (TTL, all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL, all except RSTIN and XTAL1) Input high voltage RSTIN (when operated as input) Input high voltage XTAL1 Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, RSTOUT, RSTIN2)) Output low voltage (all other outputs) Output high voltage3) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, RSTOUT) Output high voltage3) (all other outputs) Input leakage current (Port 5)
VIL
SR -0.5
VIL2 SR -0.5 0.3 VDD V VIH SR 0.2 VDD VDD + V
+ 0.9 0.5 V V V 0.5
VIH1 SR 0.6 VDD VDD + VIH2 SR 0.7 VDD VDD +
0.5
VOL
CC -
0.45
IOL = 2.4 mA
VOL1 CC - VOH CC 2.4
0.45 -
V V V V V nA nA
IOL = 1.6 mA IOH = -2.4 mA IOH = -0.5 mA IOH = -1.6 mA IOH = -0.5 mA 0 V < VIN < VDD 0.45 V < VIN < VDD VIN = VIH1 VIN = VIL VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V
0.9 VDD -
VOH1 CC 2.4
- - - -100 - -500 - 500 -
-
0.9 VDD -
IOZ1 CC Input leakage current (all other) IOZ2 CC RSTIN inactive current4) IRSTH5) RSTIN active current4) IRSTL6) RD/WR inactive current7) IRWH5) IRWL6) RD/WR active current7) ALE inactive current7) IALEL5) ALE active current7) IALEH6) IP6H5) Port 6 inactive current7)
200 500
-10 - -40 - 40 - -40
A A
A
A A A A
Data Sheet
36
V1.0, 2003-11
C161S
Electrical Parameters Table 9 Parameter Port 6 active current7) PORT0 configuration current7) XTAL1 input current Pin capacitance (digital inputs/outputs)
8)
DC Characteristics (Standard Supply Voltage Range) (cont'd) (Operating Conditions apply)1) Symbol Limit Values Min. Max. - -10 - Unit Test Condition
IP6L6) -500 IP0H5) - 6) IP0L -100 IIL CC - CIO CC -
A A A A
pF
20
10
VOUT = VOL1max VIN = VIHmin VIN = VILmax 0 V < VIN < VDD f = 1 MHz, TA = 25 C
1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current IOV. 2) Valid in bidirectional reset mode only. 3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 4) These parameters describe the RSTIN pull-up, which equals a resistance of ca. 50 to 250 k. 5) The maximum current may be drawn while the respective signal line remains inactive. 6) The minimum current must be drawn in order to drive the respective signal line active. 7) This specification is only valid during Reset and Adapt Mode. 8) Not subject to production test, verified by design/characterization.
Data Sheet
37
V1.0, 2003-11
C161S
Electrical Parameters Table 10 Parameter Input low voltage (TTL, all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL, all except RSTIN and XTAL1) Input high voltage RSTIN (when operated as input) Input high voltage XTAL1 Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, RSTOUT, RSTIN2)) Output low voltage (all other outputs) Output high voltage3) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, RSTOUT) Output high voltage3) (all other outputs) Input leakage current (Port 5) DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply)1) Symbol Limit Values Min. Max. 0.8 V - - - - - Unit Test Condition
VIL
SR -0.5
VIL2 SR -0.5 VIH SR 1.8
0.3 VDD V
VDD +
0.5
V V V V
VIH1 SR 0.6 VDD VDD +
0.5
VIH2 SR 0.7 VDD VDD +
0.5
VOL
CC -
0.45
IOL = 1.6 mA
VOL1 CC -
0.45
V V
IOL = 1.0 mA IOH = -0.5 mA
VOH CC 0.9 VDD -
VOH1 CC 0.9 VDD -
- - - -100 - -500 - 500 - -500
V nA nA
IOH = -0.25 mA
0 V < VIN < VDD 0.45 V < VIN < VDD
IOZ1 CC Input leakage current (all other) IOZ2 CC RSTIN inactive current4) IRSTH5) RSTIN active current4) IRSTL6) RD/WR inactive current7) IRWH5) IRWL6) RD/WR active current7) ALE inactive current7) IALEL5) ALE active current7) IALEH6) IP6H5) Port 6 inactive current7) IP6L6) Port 6 active current7)
200 500
-10 - -10 - 20 - -10 -
A A A A A A A A
VIN = VIH1 VIN = VIL VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max
Data Sheet
38
V1.0, 2003-11
C161S
Electrical Parameters Table 10 Parameter PORT0 configuration current7) XTAL1 input current Pin capacitance (digital inputs/outputs)
8)
DC Characteristics (Reduced Supply Voltage Range) (cont'd) (Operating Conditions apply)1) Symbol Limit Values Min. Max. -5 - Unit Test Condition
IP0H5) - IP0L6) -100 IIL CC - CIO CC -
A A A
pF
20
10
VIN = VIHmin VIN = VILmax 0 V < VIN < VDD f = 1 MHz, TA = 25 C
1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current IOV. 2) Valid in bidirectional reset mode only. 3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 4) These parameters describe the RSTIN pull-up, which equals a resistance of ca. 50 to 250 k. 5) The maximum current may be drawn while the respective signal line remains inactive. 6) The minimum current must be drawn in order to drive the respective signal line active. 7) This specification is only valid during Reset and Adapt Mode. 8) Not subject to production test, verified by design/characterization.
Data Sheet
39
V1.0, 2003-11
C161S
Electrical Parameters Table 11 Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 Power Consumption C161S (Standard Supply Voltage Range) (Operating Conditions apply) Symbol Limit Values Min. Max. 15 + mA 1.8 x fCPU 3+ mA 0.6 x fCPU 500 + A 50 x fOSC 200 + A 25 x fOSC 50 RSTIN = VIL2 fCPU in [MHz]1) RSTIN = VIH1 fCPU in [MHz]1) RSTIN = VIH1 fOSC in [MHz]1) - - - Unit Test Condition
IDD5 IIDX5 IIDO52)
Sleep and Power down mode IPDR52) supply current with RTC running Sleep and Power down mode IPDO5 supply current with RTC disabled
- -
A
VDD = VDDmax fOSC in [MHz]3) VDD = VDDmax3)
1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. 2) This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Data Sheet
40
V1.0, 2003-11
C161S
Electrical Parameters Table 12 Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 Power Consumption C161S (Reduced Supply Voltage Range) (Operating Conditions apply) Symbol Limit Values Min. Max. 7+ mA 1.2 x fCPU 1+ mA 0.4 x fCPU 300 + A 30 x fOSC 100 + A 10 x fOSC 30 RSTIN = VIL2 fCPU in [MHz]1) RSTIN = VIH1 fCPU in [MHz]1) RSTIN = VIH1 fOSC in [MHz]1) - - - Unit Test Condition
IDD3 IIDX3 IIDO32)
Sleep and Power down mode IPDR32) supply current with RTC running Sleep and Power down mode IPDO3 supply current with RTC disabled
- -
A
VDD = VDDmax fOSC in [MHz]3) VDD = VDDmax3)
1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. 2) This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Data Sheet
41
V1.0, 2003-11
C161S
Electrical Parameters
I [mA] IDD5max
100
IDD5typ
80
60
IDD3max IDD3typ
40
IIDX5max IIDX5typ
20
IIDX3max IIDX3typ
10
20
30
40
fCPU [MHz]
Figure 8
Supply and Idle Current as a Function of Operating Frequency
Data Sheet
42
V1.0, 2003-11
C161S
Electrical Parameters
I [A]
3000
IIDO5max
2500
IIDO5typ IIDO3max IIDO3typ IPDR5max
1500
1000
500
IPDR3max
IPDOmax
10 20 30 40
fOSC [MHz]
Figure 9
Sleep and Power Down Supply Current as a Function of Oscillator Frequency
Data Sheet
43
V1.0, 2003-11
C161S
Timing Characteristics
5
5.1
Timing Characteristics
Definition of Internal Timing
The internal operation of the C161S is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see Figure 10).
Phase Locked Loop Operation
fOSC
TCL
fCPU
TCL
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
TCL
MCT04338
Figure 10
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C161S. Note: The example for PLL operation shown in Figure 10 refers to a PLL factor of 4. The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
Data Sheet 44 V1.0, 2003-11
C161S
Timing Characteristics levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins P0.15-13 (P0H.7-5). Table 13 associates the combinations of these three bits with the respective clock generation mode. Table 13 CLKCFG (P0H.7-5) 111 110 101 100 011 010 001 000 C161S Clock Generation Modes CPU Frequency External Clock fCPU = fOSC x F Input Range1) Notes Default configuration - - - Direct drive2) - CPU clock via prescaler -
fOSC x 4 fOSC x 3 fOSC x 2 fOSC x 5 fOSC x 1 fOSC x 1.5 fOSC / 2 fOSC x 2.5
2.5 to 6.25 MHz 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz 6.66 to 16.67 MHz 2 to 50 MHz 4 to 10 MHz
1) The external clock input range refers to a CPU clock range of 10 ... 25 MHz (PLL operation). If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz. 2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fOSC. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fOSC for any TCL. Phase Locked Loop When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is enabled and provides the CPU clock (see Table 13). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fOSC x F). With every F'th transition of fOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs.
Data Sheet 45 V1.0, 2003-11
C161S
Timing Characteristics The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and Figure 11). For a period of N x TCL the minimum value is computed using the corresponding deviation DN: (N x TCL)min = N x TCLNOM - DN, DN [ns] = (13.3 + N x 6.3) / fCPU [MHz] where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs @ 20 MHz (i.e. N = 3): D3 = (13.3 + 3 x 6.3) / 20 = 1.61 ns, and (3TCL)min = 3TCLNOM - 1.61 ns = 73.39 ns (@ fCPU = 20 MHz). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11). (1)
Max. jitter DN ns 30 26.5 This approximated formula is valid for 1 < N < 40 and 10 MHz < fCPU < 25 MHz. -- - - 10 MHz
20 16 MHz 20 MHz 25 MHz 10
1 1 10 20 30 40
N
MCD04455
Figure 11
Approximated Maximum Accumulated PLL Jitter
Data Sheet
46
V1.0, 2003-11
C161S
Timing Characteristics Direct Drive When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fOSC x DCmin (DC = duty cycle) (2)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1, 3, ...). Timings that require an even number of TCLs (2, 4, ...) may use the formula 2TCL = 1/fOSC.
Data Sheet
47
V1.0, 2003-11
C161S
Timing Characteristics
5.2
Table 14 Parameter
External Clock Drive XTAL1
External Clock Drive XTAL1 (Operating Conditions apply) Symbol Direct Drive 1:1 Min. Max. - - - 8 8 20 5 5 - - Prescaler 2:1 Min. Max. - - - 5 5 Min. 601) 10 10 - - PLL 1:N Max. 5001) - - 10 10 ns ns ns ns ns Unit
Oscillator period High time2) Low time2) Rise time2) Fall time2)
tOSC SR 40 t1 t2 t3 t4
SR 203) SR 203) SR - SR -
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. 2) The clock input signal must reach the defined levels VIL2 and VIH2. 3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in direct drive mode depends on the duty cycle of the clock input signal.
t1 0.5 VDD t2
t3
t4 VIH2 VIL
t OSC
MCT02534
Figure 12
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is verified by design only (not tested in production).
Data Sheet
48
V1.0, 2003-11
C161S
Timing Characteristics
5.3
Testing Waveforms
2.4 V
1.8 V Test Points
1.8 V
0.45 V
0.8 V
0.8 V
AC inputs during testing are driven at 2.4 V for a logic 1' and 0.45 V for a logic 0'. Timing measurements are made at VIH min for a logic 1' and VIL max for a logic 0'. '
MCA04414
Figure 13
Input Output Waveforms
VLoad + 0.1 V
Timing Reference Points
VOH - 0.1 V
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 14
Float Waveforms
Data Sheet
49
'
' '
V1.0, 2003-11
C161S
Timing Characteristics Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. Table 15 describes, how these variables are to be computed. Table 15 Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Memory Cycle Variables Symbol Values TCL x 2TCL x (15 - ) 2TCL x (1 - )
tA tC tF
Note: Please respect the maximum operating frequency of the respective derivative.
5.4
Table 16
AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) Max. - - - - Min. TCL - 10 + tA TCL - 16 + tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - Max. - - - - - 6 TCL + 6 ns ns ns ns ns ns ns
t5 t6 t7 t8 t9 t10 t11
CC 10 + tA CC 4 + tA CC 10 + tA CC 10 + tA
CC -10 + tA - CC - CC - 6 26
Data Sheet
50
V1.0, 2003-11
C161S
Timing Characteristics Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR Max. - - 20 + tC 40 + tC 40 + tA + tC Min. Max. ns ns 2TCL - 10 - + tC 3TCL - 10 - + tC - - -
t12 t13 t14 t15 t16 t17 t18 t19 t22 t23
CC 30 + tC CC 50 + tC SR - SR - SR - SR - SR 0 SR - CC 20 + tC CC 26 + tF CC 26 + tF CC 26 + tF CC -4 - tA SR - CC 46 + tF
2TCL - 20 ns + tC 3TCL - 20 ns + tC 3TCL - 20 ns + tA + tC 4TCL - 30 ns + 2tA + tC - ns
50 + 2tA - + tC - 26 + tF - - - - 10 - tA 40 + tC + 2tA - 0 -
2TCL - 14 ns + tF ns ns ns ns ns
2TCL - 20 - + tC 2TCL - 14 - + tF 2TCL - 14 - + tF 2TCL - 14 - + tF -4 - tA - 10 - tA
ALE rising edge after RD, t25 WR Address hold after RD, WR ALE falling edge to CS1) CS low to Valid Data In1) CS hold after RD, WR1)
t27 t38 t39 t40
3TCL - 20 ns + tC + 2tA ns
3TCL - 14 - + tF
Data Sheet
51
V1.0, 2003-11
C161S
Timing Characteristics Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS Max. - - 0 Min. TCL - 4 + tA -4 + tA - Max. - - 0 ns ns ns
t42 t43 t44
CC 16 + tA CC -4 + tA CC -
t45
CC -
20
-
TCL
ns
t46 t47 t48 t49 t50 t51 t52 t54 t56
SR - SR - CC 30 + tC CC 50 + tC CC 26 + tC SR 0 SR - CC 20 + tF CC 20 + tF
16 + tC 36 + tC - - - - 20 + tF - -
- -
2TCL - 24 ns + tC 3TCL - 24 ns + tC ns ns ns ns
2TCL - 10 - + tC 3TCL - 10 - + tC 2TCL - 14 - + tC 0 - -
2TCL - 20 ns + tF ns ns
2TCL - 20 - + tF 2TCL - 20 - + tF
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
52
V1.0, 2003-11
C161S
Timing Characteristics Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Max. - - - - Min. TCL - 14 + tA TCL - 20 + tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - Max. - - - - - 6 TCL + 6 ns ns ns ns ns ns ns ns ns
t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19
CC 11 + tA CC 5 + tA CC 15 + tA CC 15 + tA
CC -10 + tA - CC - CC - CC 34 + tC CC 59 + tC SR - SR - SR - SR - SR 0 SR - 6 31 - - 22 + tC 47 + tC 45 + tA + tC
2TCL - 16 - + tC 3TCL - 16 - + tC - - -
2TCL - 28 ns + tC 3TCL - 28 ns + tC 3TCL - 30 ns + tA + tC 4TCL - 43 ns + 2tA + tC - ns
57 + 2tA - + tC - 36 + tF 0 -
2TCL - 14 ns + tF
Data Sheet
53
V1.0, 2003-11
C161S
Timing Characteristics Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Data valid to WR Data hold after WR Max. - - - - 10 - tA 47 + tC + 2tA - - - 0 Min. Max. ns ns ns ns ns 2TCL - 26 - + tC 2TCL - 14 - + tF 2TCL - 14 - + tF 2TCL - 14 - + tF -8 - tA - 10 - tA
t22 t23
CC 24 + tC CC 36 + tF CC 36 + tF CC 36 + tF CC -8 - tA SR - CC 57 + tF CC 19 + tA CC -6 + tA CC -
ALE rising edge after RD, t25 WR Address hold after RD, WR ALE falling edge to CS1) CS low to Valid Data In1) CS hold after RD, WR1) ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay)
Data Sheet
t27 t38 t39 t40 t42 t43 t44
3TCL - 28 ns + tC + 2tA ns ns ns ns
3TCL - 18 - + tF TCL - 6 + tA -6 + tA - - - 0
t45
CC -
25
-
TCL
ns
t46 t47 t48 t49
SR - SR - CC 38 + tC CC 63 + tC
20 + tC 45 + tC - -
- -
2TCL - 30 ns + tC 3TCL - 30 ns + tC ns ns
2TCL - 12 - + tC 3TCL - 12 - + tC
54
V1.0, 2003-11
C161S
Timing Characteristics Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS Max. - - 30 + tF - - Min. Max. ns ns 2TCL - 22 - + tC 0 - -
t50 t51 t52 t54 t56
CC 28 + tC SR 0 SR - CC 30 + tF CC 30 + tF
2TCL - 20 ns + tF ns ns
2TCL - 20 - + tF 2TCL - 20 - + tF
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
55
V1.0, 2003-11
C161S
Timing Characteristics
t5
ALE
t16
t25
t38
CSxL A23-A16 (A15-A8) BHE, CSxE
t39
t40
t17
Address
t27 t54 t19 t18
t6
t7
Read Cycle
BUS Address
Data In
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle
BUS Address Data Out
t23 t56 t22 t12 t50 t48
t8
WR, WRL, WRH WrCSx
t10
t42
t44
Figure 15
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
56 V1.0, 2003-11
Data Sheet
C161S
Timing Characteristics
t5
ALE
t16
t25
t38 t39
CSxL
t40
A23-A16 (A15-A8) BHE, CSxE
t17
Address
t27 t54 t19 t18
t6
t7
Read Cycle
BUS Address
Data In
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle
BUS Address Data Out
t23 t56 t22 t12 t50 t48
t8
WR, WRL, WRH WrCSx
t10
t42
t44
Figure 16
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
57 V1.0, 2003-11
Data Sheet
C161S
Timing Characteristics
t5
ALE
t16
t25
t38
CSxL
t39
t40
A23-A16 (A15-A8) BHE, CSxE
t17
Address
t27 t54 t19 t18
t6
t7
Read Cycle
BUS Address
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle
BUS Address Data Out
t23 t56 t11 t22 t13 t50 t49
t9
WR, WRL, WRH WrCSx
t43
t45
Figure 17
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
58 V1.0, 2003-11
Data Sheet
C161S
Timing Characteristics
t5
ALE
t16 t38 t39
t25
t40
CSxL
A23-A16 (A15-A8) BHE, CSxE
t17
Address
t27 t54 t19 t18
t6
t7
Read Cycle
BUS Address
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle
BUS Address Data Out
t23 t56 t9 t11 t13 t43 t45 t49 t50 t22
WR, WRL, WRH WrCSx
Figure 18
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
59 V1.0, 2003-11
Data Sheet
C161S
Timing Characteristics Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Max. - - - Min. TCL - 10 + tA TCL - 16 + tA TCL - 10 + tA -10 + tA Max. - - - - ns ns ns ns ns ns
t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18
CC 10 + tA CC 4 + tA CC 10 + tA
CC -10 + tA - CC 30 + tC CC 50 + tC SR - SR - SR - SR - SR 0 SR - - - 20 + tC 40 + tC 40 + tA + t C 50 + 2tA + tC -
2TCL - 10 - + tC 3TCL - 10 - + tC - - - - 0
2TCL - 20 ns + tC 3TCL - 20 ns + tC 3TCL - 20 ns + tA + tC 4TCL - 30 ns + 2tA + tC - ns
Data float after RD rising t20 edge (with RW-delay1)) Data float after RD rising t21 edge (no RW-delay1)) Data valid to WR
26 + - 1) 2tA + tF 10 + - 1) 2tA + tF -
2TCL - 14 ns + 22tA + tF1) TCL - 10 + 22tA + tF1) ns
SR -
t22
CC 20 + tC
2TCL - 20 - + tC
ns
Data Sheet
60
V1.0, 2003-11
C161S
Timing Characteristics Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. Data hold after WR Max. - Min. TCL - 10 + tF -10 + tF 0 + tF -4 - tA - TCL - 14 + tF TCL - 4 + tA -4 + tA - - Max. - - - 10 - tA ns ns ns ns
t24
CC 10 + tF
ALE rising edge after RD, t26 WR Address hold after WR2) ALE falling edge to CS3) CS low to Valid Data In3) CS hold after RD, WR3) ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay)1)
CC -10 + tF - CC 0 + tF CC -4 - tA SR - CC 6 + tF CC 16 + tA - 10 - tA 40 + tC + 2tA - -
t28 t38 t39 t41 t42
3TCL - 20 ns + tC + 2tA - - ns ns
t43
CC -4 + tA
-
-
ns
t46 t47 t48 t49 t50 t51 t53
SR - SR - CC 30 + tC CC 50 + tC CC 26 + tC SR 0 SR -
16 + tC 36 + tC - - - - 20 + tF
2TCL - 24 ns + tC 3TCL - 24 ns + tC ns ns ns ns
2TCL - 10 - + tC 3TCL - 10 - + tC 2TCL - 14 - + tC 0 - -
2TCL - 20 ns + 2tA + tF1)
Data Sheet
61
V1.0, 2003-11
C161S
Timing Characteristics Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. Data float after RdCS (no RW-delay)1) Address hold after RdCS, WrCS Data hold after WrCS Max. 0 + tF - - Min. - -6 + tF TCL - 14 + tF Max. TCL - 20 ns 1) + 2tA + tF - - ns ns
t68 t55 t57
SR - CC -6 + tF CC 6 + tF
1) RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral). 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
62
V1.0, 2003-11
C161S
Timing Characteristics Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Max. - - - Min. TCL - 14 + tA TCL - 20 + tA TCL - 10 + tA -10 + tA Max. - - - - ns ns ns ns ns ns
t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18
CC 11 + tA CC 5 + tA CC 15 + tA
CC -10 + tA - CC 34 + tC CC 59 + tC SR - SR - SR - SR - SR 0 SR - - - 22 + tC 47 + tC 45 + tA + t C 57 + 2tA + tC -
2TCL - 16 - + tC 3TCL - 16 - + tC - - - - 0
2TCL - 28 ns + tC 3TCL - 28 ns + tC 3TCL - 30 ns + tA + tC 4TCL - 43 ns + 2tA + tC - ns
Data float after RD rising t20 edge (with RW-delay1)) Data float after RD rising t21 edge (no RW-delay1)) Data valid to WR
36 + - 1) 2tA + tF 15 + - 1) 2tA + tF -
2TCL - 14 ns + 22tA + tF1) TCL - 10 + 22tA + tF1) ns
SR -
t22
CC 24 + tC
2TCL - 26 - + tC
ns
Data Sheet
63
V1.0, 2003-11
C161S
Timing Characteristics Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Data hold after WR Max. - Min. TCL - 10 + tF -12 + tF 0 + tF -8 - tA - TCL - 16 + tF TCL - 6 + tA -6 + tA - - Max. - - - 10 - tA ns ns ns ns
t24
CC 15 + tF
ALE rising edge after RD, t26 WR Address hold after WR2) ALE falling edge to CS3) CS low to Valid Data In3) CS hold after RD, WR3) ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay)1)
CC -12 + tF - CC 0 + tF CC -8 - tA SR - CC 9 + tF CC 19 + tA - 10 - tA 47 + tC + 2tA - -
t28 t38 t39 t41 t42
3TCL - 28 ns + tC + 2tA - - ns ns
t43
CC -6 + tA
-
-
ns
t46 t47 t48 t49 t50 t51 t53
SR - SR - CC 38 + tC CC 63 + tC CC 28 + tC SR 0 SR -
20 + tC 45 + tC - - - - 30 + tF
2TCL - 30 ns + tC 3TCL - 30 ns + tC ns ns ns ns
2TCL - 12 - + tC 3TCL - 12 - + tC 2TCL - 22 - + tC 0 - -
2TCL - 20 ns + 2tA + tF1)
Data Sheet
64
V1.0, 2003-11
C161S
Timing Characteristics Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont'd) (Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Data float after RdCS (no RW-delay)1) Address hold after RdCS, WrCS Data hold after WrCS Max. 5 + tF Min. - -16 + tF TCL - 16 + tF Max. TCL - 20 ns 1) + 2tA + tF - - ns ns
t68 t55 t57
SR -
CC -16 + tF - CC 9 + tF -
1) RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral). 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
65
V1.0, 2003-11
C161S
Timing Characteristics
t5
ALE
t16
t26
t38
CSxL
t39
t41
A23-A16 A15-A0 BHE, CSxE
t17
Address
t28 t55 t20 t18
Data In
t6
Read Cycle BUS (D15-D8) D7-D0
t8
RD
t14 t12 t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0
WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 19
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
66 V1.0, 2003-11
Data Sheet
C161S
Timing Characteristics
t5
ALE
t16 t38 t39
t26
t41
CSxL
A23-A16 A15-A0 BHE, CSxE
t17
Address
t28 t55 t20 t18
Data In
t6
Read Cycle BUS (D15-D8) D7-D0
t8
RD
t14 t12 t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0
WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 20
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
67 V1.0, 2003-11
Data Sheet
C161S
Timing Characteristics
t5
ALE
t16
t26
t38
CSxL
t39
t41
A23-A16 A15-A0 BHE, CSxE
t17
Address
t28 t55 t21 t18
Data In
t6
Read Cycle BUS (D15-D8) D7-D0
RD
t9 t15 t43 t13 t47 t49 t51 t68
RdCSx
Write Cycle BUS (D15-D8) D7-D0
WR, WRL, WRH
t24
Data Out
t9
t57 t22 t13 t50 t49
t43
WrCSx
Figure 21
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
68 V1.0, 2003-11
Data Sheet
C161S
Timing Characteristics
t5
ALE
t16 t38 t39
t26
t41
CSxL
A23-A16 A15-A0 BHE, CSxE
t17
Address
t28 t55 t21 t18
Data In
t6
Read Cycle BUS (D15-D8) D7-D0
t9
RD
t15 t13 t51 t68
t43
RdCSx
t47 t49
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t57 t9 t22 t13 t43 t50 t49
WR, WRL, WRH
WrCSx
Figure 22
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
69 V1.0, 2003-11
Data Sheet
C161S
Package Outlines
6
Package Outlines
0.25 MIN.
2.45 MAX.
0.15 +0.08 -0.02
0.88 0.15
2 +0.1 -0.05
H
0.65 12.35 0.3 0.08
C
0.1
0.12 M A-B D C 80x
17.2 14 1)
0.2 A-B D 4x 0.2 A-B D H 4x D
A
B
17.2 14 1)
80 Index Marking
1)
1 0.6 x 45
Does not include plastic or metal protrusion of 0.25 max. per side
7 MAX.
GPM05249
Figure 23
P-MQFP-80-7 (Plastic Metric Quad Flat Package)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 70 Dimensions in mm V1.0, 2003-11
www.infineon.com
Published by Infineon Technologies AG

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